1. Field of the Invention
The present invention relates to a semiconductor device having an EEPROM transistor and a Mask-ROM transistor, and methods of fabricating and forming the same.
2. Description of the Related Art
A smart card may be used as an identification card, as a credit card and as electronic cash. These uses are continuously increasing. The smart card embeds user information and transaction information and simultaneously embeds a program suitable for its purpose. Accordingly, the smart card embeds nonvolatile memory transistors for writing and storing the user information and transaction information, and includes Mask-ROM transistors for coding the program. The nonvolatile memory transistor used in the smart card is an electrically erasable programmable read-only memory (EEPROM) of a floating gate tunnel oxide (FLOTOX) type having a stable characteristic for storing information. Generally, the Mask-ROM transistor is a depletion mode or an enhancement mode Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET).
FIGS. 1 through 4 are cross-sectional views for illustrating a prior art method of forming a semiconductor device having conventional EEPROM and Mask-ROM transistors.
Referring to FIG. 1, a device isolation layer 20 is formed at a given region of a semiconductor substrate 10. The device isolation layer 20 defines a cell active region at a cell array region 1 and a Mask-ROM active region at a Mask-ROM region 2. A gate oxide layer 30 is formed on the cell active region and Mask-ROM active region. A first photoresist pattern 40 is formed on a semiconductor substrate where the gate oxide layer 30 is formed. The first photoresist pattern 40 has openings 45 exposing a given region of the cell active region and a given region of the Mask-ROM active region. The opening 45 exposing the cell active region defines a floating doped region, and the opening 45 exposing the Mask-ROM active region defines a channel doped region. An ion implantation process 50 is performed using the first photoresist pattern 40 as an ion implantation mask. Thus, the floating doped region 60 is within the cell active region and the channel doped region 65 is formed within the Mask-ROM active region.
Referring to FIG. 2, the first photoresist pattern 40 is removed, and a second photoresist pattern 70, with an opening 75 exposing the gate oxide layer 30 of the cell active region, is formed on the resultant structure. The opening 75 of the second photoresist pattern 70 exposes the gate oxide layer 30 on the floating doped region 60.
The exposed gate oxide layer 30 in opening 75 is etched using the second photoresist pattern 70 as an etch mask, to expose the floating doped region 60. In FIG. 2, the second photoresist pattern 70 covers an entire surface of the Mask-ROM region 2; thus gate oxide layer 30 and device isolation layer 20 in Mask-ROM region 2 are not etched.
Referring to FIG. 3, after the second photoresist pattern 70 is removed, a tunnel oxide layer 80 may be formed on the exposed floating doped region 60. The tunnel oxide layer 80 is formed using a thermal-oxidizing process on the exposed semiconductor substrate 10, so as to be thinner than gate oxide layer 30.
According to the prior art method, floating doped region 60 and tunnel oxide layer 80 are formed using photoresist patterns 40 and 70, respectively. Thus, a photolithographic process has to be performed two times. Misalignment may occur in a series of the photolithographic processes. If the exact alignment may be defined as an alignment performed within a tolerance limit of a processing variation, the tunnel oxide layer 80 is misaligned to the floating doped region 60 within the tolerance limit of processing variation. The misalignment may cause a non-uniform cell threshold voltage in the EEPROM, where a pair of unit cells is plane-symmetrically arranged. This is further explained below with reference to FIG. 4.
Referring to FIG. 4, after forming the tunnel oxide layer 80, memory and selection gates 92 and 94 are formed to cross over the cell active region. A common source region 85s is formed at the cell active region between a pair of the adjacent memory gates 92. A drain region 85d is formed at the cell active region between a pair of the adjacent selection gates 94. The semiconductor substrate, memory gates 92 and selection gates 94 are covered with an interlayer dielectric 96. A contact/interconnection 98 is connected to the drain region 85d through the interlayer dielectric 96.
At this time, and as described in FIG. 3, the misalignment may occur during the photolithographic processes for forming the floating doped region 60 and the tunnel oxide layer 80. Accordingly, the left cell transistor (to the left of contact/interconnection 98 in FIG. 4) is different from the right cell transistor (to the right of contact/interconnection 98 in FIG. 4) as to a distance between the floating doped region 60 and the common source region 85s (i.e., a channel length of a cell transistor). In other words, IL≠IR in FIG. 4.
Where the EEPROM cell transistors have a plane-symmetrical structure, as may be the case in FIG. 4, for example, harmful side effects resulting from the misalignment may increase. For example, in a case where δ represents an alignment variation in the processes of forming the floating doped region 60 and the tunnel oxide layer 80, a difference between the left and right channel length of the cell transistors becomes 2δ (|IL–IR|=2δ). In EEPROM cell transistors with plane-symmetrical structure, this difference (2δ) may cause a threshold voltage of the cell transistors to vary, due to band-to-band tunneling (BTBT). Direct band-to-band tunneling current is a leakage current that typically occurs where the bending of the energy band on the semiconductor substrate surface, in the vicinity of the drain region, is larger than the energy band gap of silicon in the drain region. This leakage current is generally influenced in the static mode of the semiconductor device (i.e., stand-by mode) rather than in an operational mode of the semiconductor device, and may cause the aforementioned variance in threshold voltages of the EEPROM cell transistors, for example.